What Is a Complementary FET (CFET)? Structure, Benefits, and Manufacturing Challenges
A Complementary FET (CFET) vertically stacks the n-type and p-type transistors that form CMOS logic. By moving from a side-by-side arrangement to a three-dimensional structure, CFET aims to reduce standard-cell area and improve performance and power efficiency.
From planar MOSFETs to FinFET, GAA, and CFET
Planar MOSFETs eventually faced short-channel effects as gate length decreased. FinFETs improved electrostatic control by wrapping the gate around a raised fin. Gate-All-Around (GAA) devices extend this concept by surrounding nanosheets or nanowires. CFET adds another dimension: it stacks complementary nFET and pFET devices to shrink the complete CMOS cell rather than only the individual transistor.
CFET structure and operation
In a CFET, one transistor type is fabricated above the other, with vertical connections to gates, sources, drains, power rails, and signal wiring. The devices still operate as complementary transistors, but their footprint overlaps. Several process approaches are under study, including sequential fabrication and bonding of separately processed layers.
Expected benefits
Vertical stacking can reduce cell width and wiring length, increase logic density, and lower some parasitic capacitances. Shorter interconnects may improve delay and energy efficiency. The benefit is strongest when transistor design, standard-cell layout, power delivery, and back-end wiring are optimized together.
Why CFET is being considered
At advanced nodes, interconnect resistance, routing congestion, contact placement, and power distribution increasingly limit scaling. Even if the transistor channel continues to improve, overall chip performance may not scale unless the cell and wiring architecture also change. CFET addresses this system-level density problem.
Manufacturing approaches
Sequential integration builds one device layer and then forms the second above it, requiring a strict thermal budget to avoid damaging the lower layer. Bonding approaches fabricate layers separately and join them with precise alignment. Both require accurate vertical connections, defect control, metrology, and integration with back-end-of-line processes.
Challenges toward mass production
Key challenges include process complexity, thermal budget, overlay accuracy, contact resistance, heat removal, mechanical stress, defect isolation, and yield. Vertical stacking also complicates inspection and failure analysis. The wiring architecture and power-delivery network must evolve together with the devices.
Comparison with FinFET and GAA
FinFET and GAA primarily improve gate control of a single transistor. CFET reorganizes complementary devices in three dimensions to reduce the CMOS-cell footprint. These technologies are therefore not simply alternatives: a CFET may itself use GAA-type devices in the stacked layers.
Summary
CFET represents a shift from two-dimensional transistor scaling to three-dimensional CMOS integration. Its promise is higher density and shorter wiring, while its practical success depends on alignment, contacts, thermal management, yield, inspection, and co-optimization with interconnect technology.